1. Field of the Invention
The present invention relates to digital systems. More specifically, the present invention relates to systems and methods for testing embedded hardware.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Those skilled in the art appreciate the need to test digital components and systems. Accordingly, today, many digital components and systems such as microprocessors, memory, application specific integrated circuits (ASICs) are equipped with test access ports to facilitate such testing via a test bus. The IEEE 1149.1 bus has become the industry standard test access interface for electronic components. The bus is arranged in a ring configuration where an output signal (TDOxe2x80x94Test Data Out) from one component is connected to an input signal (TDIxe2x80x94Test Data In) of another component. Each component may then be accessed individually by shifting instructions and data through registers located in each component under test. Any number of components can be chained together in this fashion. The ends of the ring are terminated at a bus controller during test. The controller drives the TDI signal on the first component in the ring and samples the data coming out of the TDO signal of the last component in the ring.
The 1149.1 test bus significantly enhances the ability of the system engineer to test individual components of the system quickly and easily. Unfortunately, the conventional 1149.1 test bus does not allow the bus controller to communicate with any components without disturbing another component on the ring that is currently under test. That is, if for example, a test is being run on a component, then other components connected to the 1149.1 ring may not be accessed as this would disturb the test running on the first component.
For certain applications, this represents a limitation that significantly increases the time required to fully validate a system under test. Take for example the startup tests for a unit in an aircraft that is composed of several modules (circuit cards) that are installed into a backplane for interconnecting their signals. Each module will have its own bus controller. These startup tests are broken into two distinct phases: 1) each module in the unit runs a self-test, and 2) all the modules cooperate to perform an interconnect test of the backplane which connects the modules together. Typically there is a strict timing requirement levied on these startup tests.
Unfortunately, some components on the modules require a large amount of time in order to attain the required xe2x80x9cfault coveragexe2x80x9d (i.e., the probability of detecting a fault). This could increase the module""s self-test time such that there would not be enough time left to perform the backplane interconnect test. Thus, there is a need to separate the components that have long self-test times from those that are used to perform the backplane interconnect test so they can be run in parallel. Hence, designers are currently forced to position components having long test times on one 1149.1 bus ring and components used in the backplane interconnect test on another. Those that do not fall into either category can be placed on either ring. However, this multi-ring approach does not lend itself to the use of commercial off-the-shelf (COTS) software test generation tools as these tools require the components being tested to be on a single ring.
Accordingly, a need exists in the art for a system or technique that allows the components to be on a single ring for tests generated by COTS tools, but also allows a separation of components onto separate rings in order to allow parallelism as described in the above example.
The need in the art is addressed by the programmable interface of the present invention. The inventive interface is designed to be used with an 1149.1 bus controller and includes a first circuit for selecting one or more components from a plurality of components in response to at least one first control signal. A second circuit selectively connects the components in response to at least one second control signal. A third circuit selects a serial output mode or a parallel output mode of said components in response to at least one third control signal.
In an illustrative implementation, the inventive interface is used as part of an IEEE 1149.1 bus architecture and includes a plurality of identical stages, each one cascading into the next. Each stage is associated with a ring of zero or more components, preferably only one, and includes circuitry for selecting the associated component(s). The second circuit includes circuitry within each stage for selectively connecting the associated component(s) to a second component ring associated with another stage. The third circuit includes circuitry disposed within each stage for outputting the output of the associated component ring or the output of another component ring as the output of the stage. The first, second and third control signals are provided by the interface controller.
The inventive interface thereby provides a system and technique for conducting tests of components in an 1149.1 environment on a single ring so that standard COTS test generation tools can be used, and allowing communication with some components while run-based commands are being executed on other components so that parallel activities can be performed.